1. Field of the Invention
This invention relates to an insulated-gate type of semiconductor device and, in particular, to a technique of implementing a high avalanche capability in a power metal-oxide-semiconductor field-effect transistor (MOSFET).
2. Description of Related Art
When an inductive load is driven by a power MOSFET, the inductive counter electromotive force at turned-off (hereinafter called an "inductive kick") leads to breakdown of the power MOSFET, which is called avalanche failure. This avalanche breakdown occurs when parasitic bipolar transistors in the power MOSFET are activated by the breakdown current.
An example of a conventional vertical power MOSFET having trench gates is shown in FIGS. 10 and 11, where FIG. 10 is a partial plan view thereof without an insulated film over the source electrodes and trench gates and FIG. 11 is a partial cross-sectional view of essential components thereof.
This power MOSFET has an n.sup.+ -type semiconductor substrate 1 as well as an n-type epitaxial layer 2, a p-type body layer 3, an n.sup.+ -type source region 4, a gate insulated film 5, gate electrodes 6, a source electrode 7, and a drain electrode 8. In the source region 4, contact regions 9 for the body layer 3 are formed by exposed portions of the body layer 3 that are disposed as islands. In FIG. 11, reference symbol "I.sub.ON " denotes an on current and "I.sub.B " denotes the breakdown current generated when the MOSFET is turned off. Reference symbol "Q" denotes a parasitic npn bipolar transistor and reference symbol "R.sub.B " denotes the parasitic resistance of the body layer 3.
When this MOSFET is turned off, the breakdown current I.sub.B flows because of the inductive kick. This breakdown current I.sub.B flows from the drain electrode 8 through the semiconductor substrate 1, the epitaxial layer 2, the body layer 3, and the contact regions 9 to the source electrode 7. During this time, if the voltage drop generated between the two ends of the resistance R.sub.B of the body layer 3 exceeds the voltage V.sub.BE between the base and emitter of each parasitic bipolar transistor Q, the parasitic bipolar transistor Q may turn on and an over-large breakdown current may concentrate through the transistor Q, so that junction destruction or melting of the silicon or the wiring may occur, resulting in the element destruction.
When power MOSFETs are used in automotive applications in particular, a large proportion of the vehicle-mounted loads are inductive loads due to motors or solenoid valves, so it is extremely important to avoid the danger of avalanche failure caused by inductive kicks.
Up to the present, various methods of suppressing the operation of these parasitic bipolar transistors have been taken to avoid this avalanche failure. More specifically, one of the following methods is used in n-channel power MOSFETs (by way of example) in order to reduce the resistance of the body layer that is equivalent of the base resistance of each parasitic bipolar transistor: (a) a deep, high-impurity concentration p-type diffused region is formed in the semiconductor layer between adjacent gate electrodes, or (b) the body layer is made to be deeper.
Of these conventional countermeasures, a method (a), in which a deep, high-impurity concentration p-type diffused region is formed between adjacent gate electrodes, has problems as discussed below.
1. Ordinarily, to form the p-type diffused region so as to surround an n-type source region that has a higher impurity concentration than the P-type diffused region, it is necessary to secure a sufficiently large surface area for the p-type region from consideration of possible lateral diffusion of the n-type impurity forming the source region. This means that the method (a) limits a reduction in size of the element and prevents any reduction in the on-resistance of the power MOSFET. PA0 2. If the impurity of the p-type diffusion region is diffused as far as the channel region formed in the immediate vicinity of the gate electrode, the threshold voltage of the power MOSFET will increase. For that reason, the method (a) limits a reduction in size of the element and prevents any reduction in the on-resistance (drain-source on-state resistance) of the power MOSFET, in a similar manner to the above. PA0 3. If the body layer is deeper in a vertical power MOSFET having trench gates, this leads directly to an increase in the channel length, which leads to an increase in the channel resistance, in other words, the on-resistance. With a vertical power MOSFET of a planar gate structure, deepening the body layer causes broadening in both the depthwise direction and the widthwise direction, which leads to an increase in the channel resistance, in other words, the on-resistance.
A method (b), in which the body layer is made deeper, also has problems as discussed below.
There is thus a trade-off in the conventional structure between reducing the on-resistance and increasing the avalanche capability, and it is difficult for the conventional structure of a device to satisfy these two requirements adequately.